IBM corp. introduced flip chip package technique in early 1960, the flip chip technique differs from the earlier wire bonding technique in that electrical connections between a semiconductor chip and a circuit board are established through solder bumps rather than traditional gold wires. Advantages of the flip chip technique are increased packaging density and reduced package size. Additionally, the flip chip technique requires no metal conductive wires, thus enhancing electrical properties and satisfying the needs for high-density and high-speed semiconductor devices.
In current flip chip technique, electrode pads are disposed on an active face of a semiconductor IC chip, and corresponding electrode pads are also provided on the circuit board for carrying the chip. Solder bumps or other conductive adhesives can be appropriately disposed between the chip and the circuit board, so that the active face of the chip is connected face down on the circuit board, wherein the electrical and mechanical connections between the chip and the circuit board are provided through the solder bumps or conductive adhesives.
FIG. 1 shows a Flip Chip Ball Grid Array (FCBGA) packaging structure in U.S. Pat. No. 6,774,498. A semiconductor chip 10 comprises an active surface, on which electrode pads 101 for signal input and output are provided. Metal bumps 11 are formed on the electrode pads 101 and electrically connected to electrical connecting pads 121 of a circuit board 12. The circuit board is formed with a plurality of wiring layer 122 and insulating layers 123; conductive structures 125 are connected between two wiring layers 122. On the uppermost wiring layer 122 of the circuit board 12 is formed with a solder mask 13 to protect the wiring layer 122 while expose the electrical connecting pads 121. Conductive structures such as solder balls 14 are formed on the electrical connecting pads 121, completing the FCBGA packaging structure. However, during the fabrication process of the FCBGA package, the circuit board 12 is separately fabricated from the process of electrically connecting the semiconductor chip 10 to the circuit board 12 for packaging. In other words, the circuit board is an independent process, while connecting the semiconductor chip 10 to the circuit board 12 is another independent process. These two processes being independently implemented results in uneven quality in production and long production cycle, and its electrical properties can only reach certain levels but cannot be further improved. Moreover, although the FCBGA structure can be utilized in high pin count and high frequency products, but the overall cost of packaging is high and the technique still faces with many limitations, especially in the electrical connections. Due to environmental concerns, conventionally used soldering materials for electrical connections, such as lead (Pb), are banned, and instead alternative materials with less desirable electrical, mechanical and physical properties are used.
Additionally, during the fabrication of flip chip semiconductor device, after a wafer IC fabrication step, an Under Bump Metallurgy (UBM) structure layer is formed on the electrode pads of the chips in the wafer for carrying metal bumps, then a singulation process is performed to segment the wafer into a plurality of single chips, then each semiconductor chip is electrically connected to a circuit board, wherein the fabrication processes for the UBM structure layer and the metal bumps are very expensive and complex.
Thus, for a flip chip semiconductor device that requires corresponding electrical connecting units (e.g. metal bumps and pre-soldering bumps) to be respectively formed on the semiconductor chip and the corresponding circuit board, it not only increases the number of fabrication steps and cost, but also reduces the reliability of the fabrication.
Moreover, the aforementioned semiconductor packaging structure is directly adhere to the topmost area of the circuit board and encapsulated with gel, and the bottom surface of the circuit board is mounted with solder bumps. Such a vertical stacking structure increases the overall height. In addition, when the semiconductor chip is sealed with the gel, it can no longer make other connections, such as for chip stacking or circuit board stacking, thereby reducing the flexibility in application of the packaged products.
Furthermore, under the trend for high-functionality and high-speed electronic products, passive components such as resistors, capacitors, and inductors are required to be integrated into the semiconductor package to increase or stabilize the electrical functionalities of the electronic products. However, these passive components are usually mounted on the surface of the circuit board, conventionally on the corners of the circuit board or additional layout areas outside the semiconductor connecting region of the circuit board to prevent blocking the electrical connection of bonding fingers between the semiconductor chip and the circuit board. However, limiting the passive components reduces the routability of wires on the surface of the circuit board. The number of the passive components is also limited concerning locations of the bonding fingers. Following the demands for high functionality of the semiconductor package, the number of passive components is increased accordingly, which will forcibly increase the package size to accommodate for large numbers of semiconductor chips and passive components.